Minutes, IBIS Quality Committee

27 November 2012

11:00-12:00 EST (08:00-09:00 PST)

ROLL CALL

Altera				    David Banas
Cadence Design Systems:           * Joy Li
                                  * Yingxin Sun
Cisco Systems:                      Tony Penaloza
Ericsson:                         * Anders Ekholm
Green Streak Programs:              Lynne Green
Huawei Technologies:                Guan Tao
IBM:                                Bruce Archambeault
                                    Greg Edlund
Intel                             * Michael Mirmak
IOMethodology:                    * Lance Wang
Mentor Graphics:                    John Angulo
Micron Technology:                  Moshiul Haque,
                                    Randy Wolff
Nokia Siemens Networks:             Eckhard Lenski
QLogic Corp.:                       James Zhou
Signal Consulting Group:            Tim Coyle
Signal Integrity Software         * Mike LaBonte
Teraspeed Consulting Group:       * Bob Ross
Texas Instruments:                  Pavani Jella

Everyone in attendance marked by *

NOTE: "AR" = Action Required.

-----------------------MINUTES ---------------------------
Mike LaBonte conducted the meeting.

Call for opens and IBIS related patent disclosures:

- With two new joiners we all introduced ourselves:
  - Joy Li: Product Engineer for Cadence SPEED2000 product line
    - Working in Dallas, TX
  - Yingxin Sun: Developer for IBIS model simulation
  - Anders: Ericsson SI expert
  - Lance: IOMeth, previously Cadence. Modeling service
  - Mike L: Marketing at SiSoft
  - Bob: Formerly MGC, former IBIS chair
  - Michael M: IBIS chair, Intel customer solutions

AR Review:

- None

New items:

- Joy showed a presentation "Golden Parser's Non-Monotonic Warning Investigation"
- Slide 1:
  - The T2D tool uses the IBIS parser
  - Non-monotonic warnings are false
  - Models still can be used, but the warnings are uncomfortable to users
- Slide 2:
  - Example of warning message
  - Bob: What is VDD?
  - Joy: 1.25V
- Slide 3:
  - Combined PullDown is sum of PullDown + clamp
- Slide 4:
  - Anders: What is the red curve at the bottom?
  - Joy: An attempt to interpolate smoothly
  - Anders: The parser seems to be doing the right thing:
  - MM: Where is that in IBIS?
  - Bob: tools can be more precise
    - spline fitting for example
    - This looks like a 1.8V device
  - Mike: Spline should be acceptable
- Slide 5:
  - The parser interpolation is probably lower than actual
  - Interpolated points may be differing from original points
  - Yingxin: 
- Slide 6:
  - Zoomed in view showing the non-monotonic data
- Slide 7 & 8:
  - Second example of the issue
- Slide 9:
  - Bob: There may be some double counting of the clamp
  - Yingxin: No it is from the original points combined
  - Lance: The clamp current is a lot larger than the Pullup
    - You subtract clamps from combined to get PullDown
    - More points near the key voltages will make it smoother
    - It is more of a problem where the Pullup goes down and clamp goes up
  - Yingxin: This is a problem of point alignment
  - Mike: If point interval is 0.1V and min/max are off 0.15V they will not be aligned
  - Bob: It is not stated, but these are max curves
  - Lance: Is there a tolerance value for the non-monotonic warning?
    - Very small values should not be reported
- Slide 10:
  - Mike: Is this data from internal parser code?
  - Yingxin: No it is from original data, processed same as the parser
- Slide 11:
  - Anders: This is a specification issue
    - It is not specified how to interpolate
  - Mike: Is the limit for I/V curves still 100?
  - Bob: Yes
  - MM: Do we want to state what interpolation the parser uses?
    - Should there be options for that?
    - The parser has greater power than the spec
  - Lance: That may not solve anything if there are not enough points
  - Mike: It should be possible to predict the voltage points needed to line up
    - Although adding more points to one curve necessitates more points in the others
  - Bob: The max and min can have NAs for that
  - Anders: If PWL is wrong we should specify that
    - But other methods may introduce other errors
  - MM: Should there be a check for sufficient points?
  - Mike: There is an IQ check for that
  - Anders: We could check for points that are sufficient and aligned
  - Mike: All EDA tools probably use splines to combine curves
  - Bob: Some use decomposed curves for simulation
  - Lance: This might be changed to INFO, not WARNING
  - Bob: People may pay no attention
    - I would like to see the raw data for this
  - Mike: Is there a spreadsheet for the data?
  - Joy: We need to check with the customer
  - Bob: Only the I/V tables would be needed

Mike: To file a parser bug we will need a testcase IBIS file
- It can be minimal and fake
- Bob: Minimal contrived examples are best
- Lance: I don't see this as a bug
- Anders: It could be an algorithm issue

AR: Joy and Yingxin work with Bob and Mike to possibly file parser bug

Review of group meeting schedule:

Next meetings:
- The next two meetings will be Dec 11 and Jan 8

- Meeting ended at 11:57 ET